Phase-locked loops (“PLLs”) are commonly used to support the generation of sampling clocks for data recovery in high speed data transmission systems. As data rates continue to rise, the ability to accurately control the sampling point of the clock is becoming increasingly complex. Current solutions support placing the clock at a location optimal for sampling the data based on the location of the data transition. Some existing systems allow the sampling clock to be offset in the data sampling window, but these systems use power-consuming circuits beyond the source point of the clock generation.
As serializer/deserializer (“SERDES”) data rates increase, a horizontal opening of a transmitted eye of a data stream decreases. At these higher data rates, the point at which the eye is sampled becomes more critical due to the non-optimum shape of the eye. The eye is distorted due to behavior of transmit circuitry as well as a lossy channel the eye is transmitted across. In one example, an optimum sampling point is at the midpoint of the eye. In practice, the eye is often distorted, thereby shifting the optimum sampling point away from the midpoint.